UCCE2053 Computer Organisation and Architecture Assignment Sample 2026

UCCE2053 Assignment Sample

Assignment Type : Practical Assignment
Pipeline Processor Design: Specification Development

1. Architecture Specification: Written Spec

1.1 Functionality / Feature

• 32-bit MIPS ISA-compatible CPU processor.
• System Verilog-based design.
• Supports a 5-stage pipeline:
  o Instruction Fetch (IF)
  o Instruction Decode and Operand Fetch (ID)
  o Instruction Execute (EX)
  o Memory Access (MEM)
  o Register Write Back (WB)
• Contains 32 general-purpose registers.
• Supports Program Counter (PC) for instruction sequencing.
• Supports instruction and data memory interfaces.
• Supports Memory Read / Write Operations: lw, sw, lb, and sb.
• Performs Arithmetic, Logical, Comparison and Address-Generation Operations.
• Supports Branch Instructions: beq, and bne.
• Supports Jump Instructions: j, and jal.
• Supports the selected Group 3 instructions: l_inc and R-format lw variant.  Supports Pipeline Hazard Management.

1.2 Operating Procedure and Application

1.2.1 Programming Mode

• MIPS assembly code is converted into machine code before execution.  The verification process follows the general flow:
• Machine code is then stored in a file and loaded into instruction memory.

1.2.2 Normal Execution Mode

1. The PC provides the instruction address.
2. The instruction is fetched from instruction memory.
3. The instruction is decoded and source operands are obtained.
4. The ALU performs arithmetic, logical, comparison, shift, or address-generation operations.
5. Memory access is performed when required.
6. The selected result is written back to the register file.

1.3 Naming Convention

1.4 Pipeline Chip Interface and I/O Pin Description

1.4.1 Pipeline Chip Interface 

1.4.2 I/O Pin Description

1.4.3 Timing Diagram  

1. Programming Mode Timing (prog_en = 1)
Setup Requirement: prog_addr and prog_data must be driven valid before the rising edge of clk.
Latch Timing: prog_we pulses high for one clock cycle to latch prog_data into Instruction Memory at address prog_addr.

2. Normal Execution Mode Timing (prog_en = 0)

Reset Sequence: On rst falling edge at T0, PC clears to 0x0000_0000 and outputs pc_out.

• Instruction Fetch (IF): instr_addr matches pc_out. Instruction Memory returns instr_data within the same clock cycle.
• Memory Read (MEM): During load instructions (lw) at T4, data_re asserts high, placing memory contents onto data_rdata.

1.5 Internal Operation

1.5.1 Instruction Fetch (IF)

• Inputs and Control Signals: PC (Program Counter), clk, rst, PC Control/Stall flags.
• Stage Operations: o Memory Fetch: Drives instr_addr with PC [31:0] to retrieve the 32-bit instruction word (instr_data) from Instruction Memory. o Next PC Calculation: Computes PC + 4 as the normal sequential instruction address (or selects branch/jump target addresses when branch control flags are asserted).
• Output Pipeline Register (IF_ID): Latches instr_data and computed PC + 4 on the rising clock edge.

1.5.2 Instruction Decode and Operand Fetch (ID)

• Input Pipeline Register: Incoming data from IF_ID (instr_data, PC + 4), Register File data outputs, Hazard/Stall control flags.
• Stage Operations:
  • Instruction Decoding: Decodes opcode, funct, and register fields (rs, rt, rd).
  • Register File Read: Reads source operands (R[rs] and R[rt]) from the register file.
  • Immediate Extension and Control: Performs sign/zero extension on the 16-bit immediate field and generates execution, memory, hazard, and write_back control signals.
• Output Pipeline Register: Latches control signals, read data (rs_data, rt_data), signextended immediate, target register indices, and PC + 4 into ID_EX.

 1.5.3 Instruction Execute (EX)

• Inputs and Control Signals: Incoming data from ID_EX, hazard forwarding paths (forwardA, forwardB).
• Stage Operations: o Standard Operations: Performs ALU arithmetic, logical, shift, and comparison operations using forwarding multiplexers. Calculates branch targets and standard base + offset memory addresses.
  • Group 3 l_inc Extension: Calculates effective memory address while simultaneously evaluating secondary base increment value R[rs] + 4.
    Address = R[rs] + SignExt(imm)
    R[rt]      = Memory[Address] R[rs]      = R[rs] + 4
  • Group 3 R-format lw Variant Extension: Calculate the effective memory address by using two register operands via the ALU.
    Address = R[rs] + R[rt]
    R[rd]     = Memory[Address]

• Output Pipeline Register (EX_MEM): Latches ALU results, store data (R[rt]), secondary increment values (l_inc), target register indices, and memory/WB control signals into EX_MEM.

1.5.4 Memory Access (MEM)

• Inputs and Pipeline Register: Incoming data from EX_MEM, memory read bus (data_rdata).
• Stage Operations:
  o Memory Address and Control: Drives data_addr using the ALU execution result. Asserts data_re for load indtructions or data_we for store instructions.
  o Data Transfer: Passes store data (data_wdata) from the forwarded register value into Data Memory during stores and captures incoming read data (data_rdata) during loads.
• Output Pipeline Register (MEM_WB): Latches data_rdata, ALU execution outputs, secondary increment values (l_inc), target register indices, and write-back control signals into MEM_WB.

1.5.5 Register Write Back (WB)

• Inputs and Pipeline Register: Incoming data from MEM_WB, clk, rst.
• Stage Operations: o Result Selection: Multiplexes the final write-back value from either the ALU execution result or memory read data (data_rdata).
  • Standard Write-Back: Writes the selected result to the destination register (rd or rt) on the falling clock edge.
  • Group 3 Dual Write-Back (l_inc): Updates destination register rt with loaded memory data while simultaneously updating base register rs with the secondary incremented value (R[rs] + 4).
• State Update: Updates the Register File contents for subsequent instruction cycles.

1.6 Memory Map

 Byte-to-Word Address Mapping Note

The Boot ROM occupies byte address range 0x0000_0000 through 0x0000_003C (64 bytes total) because the internal array structure stores 32-bit words, simulation initialization loaded via $readmemh targets word indices 0 through 15. The address conversion follows:

Word_Index = [Byte_Address / 4]

1.7 System Registers

The CPU contains the following main architectural registers.

 Special Register Behaviour  $zero is hardwired to 32’b0.

• Any attempt to write to $zero does not change its value.
• $ra is automatically selected as the destination register for the jal instruction.
• The remaining registers can be used as source or destination registers according to the supported instruction format.

1.8 Supported Instruction Description

 1.9 Addressing Mode

 2. Micro-Architecture Specification

2.1 Design Hierarchy

1. Top Level

1. Block Level

2.2 Pre-Synthesis Unit Level Schematic

3. Architecture Specification: Verification Spec

1 Test Programmes and Binaries

3.1.1 Individual Instruction Test Program

 3.1.2 Basic Building Block Tests

3.1.3 Data Hazard Test Program

3.2 Integration Test Program

The program is designed to verify that different processor functions operate correctly together in the five-stages pipeline.

3.3 Boot Program and Program Loading Specification

3.3.1 Boot Program

Upon reset assertion (reset = 1), the Program Counter (PC) is initialized to 0x00000000 (Boot ROM address space) and all internal pipeline registers are flushed (IF_ID, ID_EX, EX_MEM, MEM_WB). The boot load clears pipeline registers and initializes stack pointers before jumping to 0x0000_0040 (Text Segment).

As shown in the boot sequence flow diagram, execution follows a deterministic initialization path:

1. Reset State: Holds PC = 0x0000_0000 and forces control signals to zero.
2. Boot ROM Fetch: Fetches setup instructions from the Boot ROM space (0x0000_0000 to 0x0000_003C).
3. Pipeline and State Init: Clears hazard units, zeros register file register, and sets initial stack pointers.
4. Application Handoff: Executes an unconditional jump (j 0x0000_0040) to transfer control to the user application program in the text segment.

 3.3.2 Program Loading Specification

1. Memory Region Allocation

 2. HDL Memory Initialization

In SystemVerilog simulation, instruction memory (imem) is pre-loaded using $readmemh system tasks. The machine code generated by the assembler is formatted into standard ASCII 32-bit hexadecimal strings.

 Execution Parameters and Rules

• Address Translation: Array indices 0..1023 represent 32-bit word addresses indexed using word aligned addressing (PC [31:2]).
• Simulation Requirements: boot.hex and program.hex must be placed in the simulator’s root working directory.
• Format Specification: Hex files must contain raw 8-difit hexadecimal instructions (e.g., 20080005) separated by line breaks, without 0x prefixes.

 4. Micro-Architecture Secification: Unit And Block Levels

4.1 CPU Unit

4.1.1 Functionality / Feature

• Maintains the Program Counter.
• Fetches instructions from instruction memory.
• Transfers instructions through the five-stages pipeline.
• Reads source operands from the register file.
• Selects ALU operands using multiplexers.
• Performs execution and address-generation operations.
• Transfers data between the processor and data memory.
• Selects the appropriate write-back result.
• Supports pipeline hazard handling.
• Supports l_inc and R-format lw variant.

  4.1.2 CPU Unit Interface and I/O Pin Description

1. CPU Unit Interface
2. I/O Pin Description

 4.1.3 Internal Operation

Program Counter

• Stores the current instruction address.
• Normally updates to PC + 4.
• Supports branch and jump target selection.
• Updated on the active clock edge.
• Pipeline Registers